Display apparatus

ABSTRACT

A display apparatus is provided which is capable of improving display quality by expanding the light-emission area of pixels by improving the layout of pixels and common power-feed lines formed on a substrate. Pixels including a light-emission element, such as an electroluminescence element or an LED element, are arranged on both sides of common power-feed lines so that the number of common power-feed lines is reduced. Further, the polarity of a driving current flowing between the pixels and the light-emission element is inverted so that the amount of current flowing through the common power-supply lines is reduced.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an active-matrix-type display apparatuswhich uses light-emission elements, such as EL (electroluminescence)elements that emit light when driving current flows through an organicsemiconductor film or LED (light-emitting diode) elements, and thin-filmtransistors (hereinafter referred to as “TFTs”) that control thelight-emission operation of this light-emission element. Moreparticularly, the present invention relates to layout optimizationtechnology for improving the display characteristics thereof.

2. Description of Related Art

Active-matrix-type display apparatuses which use current-control-typelight-emission elements, such as EL elements or LED elements, have beenproposed. Since any of the light-emission elements used in this type ofdisplay apparatus may emit light by itself, unlike a liquid-crystaldisplay device, a back light is not required, and there are advantagesin that viewing angle dependence is small.

FIG. 22 shows, as an example of such a display apparatus, a blockdiagram of an active-matrix-type display apparatus which usescharge-injection-type organic thin-film EL elements. In a displayapparatus 1A shown in this figure, formed on a transparent substrate area plurality of scanning lines “gate”, a plurality of data lines “sig”extending in a direction intersecting the extension direction of thesescanning lines “gate”, a plurality of common power-feed lines “com”which are parallel to these data lines “sig”, and pixels 7 correspondingto the intersections of the data lines “sig” and the scanning lines“gate”. With respect to the data lines “sig”, a data-side drivingcircuit 3 comprising a shift register, a level shifter, video in, and ananalog switch is formed. With respect to the scanning lines, ascanning-side driving circuit 4 comprising a shift register and a levelshifter is formed. Further, each of the pixels 7 is formed with a firstTFT 20 in which a scanning signal is supplied to its gate electrode viathe scanning lines, a holding capacitor “cap” for holding an imagesignal supplied from the data lines “sig” via this first TFT 20, asecond TFT 30 in which an image signal held by this holding capacitor“cap” is supplied to its gate electrode, and light-emission elements 40to which driving current flows from the common power-feed lines “com”when these are electrically connected to the common power-feed lines“com” via the second TFT 30.

Specifically, as shown in FIGS. 23(A) and 23(B), in all the pixels 7,the first TFT 20 and the second TFT 30 are formed using twoisland-shaped semiconductor films, a relay electrode 35 is electricallyconnected to the source and drain regions of the second TFT 30 via acontact hole of a first interlayer insulation film 51, and a pixelelectrode 41 is electrically connected to the relay electrode 35 via acontact hole of a second interlayer insulation film 52. On the side ofthe upper layers of this pixel electrode 41, a positive-hole injectionlayer 42, an organic semiconductor film 43, and a counter electrode “op”are multilayered. Here, the counter electrode “op” is formed over aplurality of pixels 7 in such a manner as to extend across the datalines “sig” and the like. Further, the common power-feed lines “com” areelectrically connected to the source and drain regions of the second TFT30 via the contact hole.

In contrast, in the first TFT 20, a potential holding electrode “st”which is electrically connected to the source and drain regions iselectrically connected to an extended portion 310 of a gate electrode31. On the side of the lower layers thereof, a semiconductor film 400opposes this extended portion 310 via a gate insulation film 50, andsince this semiconductor film 400 is made to conduct by impuritiesintroduced thereinto, this semiconductor film 400, together with theextended portion 310 and the gate insulation film 50, constitute theholding capacitor “cap”. Here, the common power-feed line “com” iselectrically connected to the semiconductor film 400 via the contacthole of the first interlayer insulation film 51. Therefore, since theholding capacitor “cap” holds an image signal supplied from the datalines “sig” via the first TFT 20, even if the first TFT 20 is turnedoff, the gate electrode 31 of the second TFT 30 is held at a potentialcorresponding to the image signal. Therefore, since the driving currentcontinues to flow to the light-emission element 40 from the commonpower-feed lines “com”, the light-emission element 40 continues to emitlight.

However, in comparison with the liquid-crystal display apparatus, in thedisplay apparatus 1A, there is a problem in that the display qualitycannot be improved because the pixels 7 are narrower by an amountcorresponding to the requirement of the second TFT 30 and the commonpower-feed lines “com”.

SUMMARY OF THE INVENTION

Accordingly, an object of the present invention is to provide a displayapparatus capable of improving display quality by expanding thelight-emission area of pixels by improving the layout of pixels andcommon power-feed lines formed on a substrate.

In order to solve the above-described problems, the present inventionprovides a display apparatus comprising on a substrate: a plurality ofscanning lines; a plurality of data lines extending in a directionintersecting the extension direction of the scanning lines; a pluralityof common power-feed lines parallel to the data lines; and pixels formedin a matrix by the data lines and the scanning lines, each of the pixelscomprising: a first thin-film transistor in which a scanning signal issupplied to its first gate electrode via the scanning lines; a holdingcapacitor for holding an image signal supplied from the data lines viathe first thin-film transistor; a second thin-film transistor in whichthe image signal held by the holding capacitor is supplied to its secondgate electrode; and a light-emission element having an organicsemiconductor film, which emits light by driving current that flowsbetween a pixel electrode and a counter electrode when the pixelelectrode is electrically connected to the common power-feed line viathe second thin-film transistor in a section between the layers of thepixel electrodes formed for each of the pixels and the counterelectrodes opposing the pixel electrodes, wherein pixels in which thedriving current is passed in a section between the pixels and the commonpower-feed lines are arranged on both sides of the common power-feedlines, and the data lines pass on a side opposite to the commonpower-feed lines with respect to the pixels.

Specifically, in the present invention, since a data line, a group ofpixels connected thereto, one common power-feed line, a group of pixelsconnected thereto, and a data line for supplying a pixel signal to thegroup of pixels are assumed to be one unit and this is repeated in theextension direction of scanning lines, pixels for two rows are driven byone common power-feed line. Therefore, the formation area of commonpower-feed lines can be made more narrow than in a case in which acommon power-feed line is formed for each group of pixels for one row,the light-emission area of the pixels can be expanded correspondingly.Therefore, it is possible to improve display performance, such asluminance, contrast ratio, and so on.

When the construction is formed in this manner, it is preferable that,for example, in a section between two pixels arranged in such a manneras to sandwich the common power-feed line, the first thin-filmtransistor, the second thin-film transistor, and the light-emissionelements be disposed in linear symmetry about the common power-feedline.

In the present invention, also, it is preferable that the pitch of thecenters of the formation areas of the organic semiconductor films beequal at every interval between adjacent pixels along the extensiondirection of the scanning lines. When the construction is formed in thismanner, it is convenient to cause a material for an organicsemiconductor film to be discharged from an ink-jet head and to form anorganic semiconductor film. That is, since the pitch of the centers ofthe formation areas of the organic semiconductor films is equal, thematerial for an organic semiconductor film may be discharged from theink-jet head at even intervals. This simplifies the movement controlmechanism of the ink-jet head, and the position accuracy is improved.

Further, it is preferable that the formation area of the organicsemiconductor film be surrounded by a bank layer formed from aninsulation film thicker than the organic semiconductor film, and thatthe bank layer be formed in such a manner as to cover the data lines andthe common power-feed line at the same width dimension. When theconstruction is formed in this manner, since the bank layer prevents theextrusion of the organic semiconductor film into its periphery when theorganic semiconductor film is formed by an ink-jet method, the organicsemiconductor film can be formed within a predetermined area. Further,since the bank layer covers the data lines and the common power-feedline at the same width dimension, this is suitable for making the pitchof the centers of the formation areas of the organic semiconductor filmsequal at any interval of the adjacent pixels along the extensiondirection of the scanning lines. Here, the counter electrodes are formedat least on nearly the entire surface on the pixel area or over a widearea in a stripe form, and are in a state of opposing the data lines.Therefore, if kept in this state, a large capacitance parasitizes thedata lines. However, in the present invention, since a bank layer isinterposed between the data lines and the counter electrodes, it ispossible to prevent parasitization of the capacitance formed in asection adjoining the counter electrodes into the data lines. As aresult, since the load in the data-side driving circuit can be reduced,power consumption can be reduced or a higher-speed display operation canbe achieved.

In the present invention, it is preferable that a wiring layer be formedat a position corresponding to a section between two data lines passingon a side opposite to the common power-feed line with respect to thepixels. When two data lines are parallel to each other, there is a riskthat crosstalk may occur between these data lines. However, in thepresent invention, since another wiring layer different from thosepasses between two data lines, the crosstalk can be prevented by merelymaintaining such a wiring layer at a fixed potential at least within onehorizontal scanning period of the image.

In this case, between two adjacent data lines of the plurality of datalines, it is preferable that sampling of an image signal be performed atthe same timing. When the construction is formed in this manner, sincepotential variations during sampling occur simultaneously in a sectionbetween two data lines, it is possible to more reliably prevent anoccurrence of crosstalk between these data lines.

In the present invention, it is preferable that nearly the same numberof pixels of two types, in which the light-emission elements are drivenby a driving current whose polarity is inverted, be among the pluralityof pixels in which the driving current is passed in a section betweenthe pixels and the common power-feed lines.

When the construction is formed in this manner, the driving currentwhich flows from the common power-feed line to the pixels cancels thedriving current which flows from the pixels to the common power-feedline, thereby a smaller amount of driving current which flows throughthe common power-feed line is required. Therefore, since the commonpower-feed lines can be made narrow correspondingly, it is possible toexpand the display area with respect to the panel exterior. It is alsopossible to eliminate luminance variations which occur due to adifference between driving currents.

For example, the construction is formed in such a way that the polarityof the driving current in each pixel is the same in the extensiondirection of the data lines and that, in the extension direction of thescanning lines, the polarity of the driving current in each pixel isinverted for each pixel or every two pixels. The construction may alsobe formed in such a way that the polarity of the driving current in eachpixel is the same in the extension direction of the scanning lines andthat, in the extension direction of the data lines, the polarity of thedriving current in each pixel is inverted for each pixel or every twopixels. Of these constructions, in the case of the construction in whichthe polarity of the driving current is inverted every two pixels, forthe pixels through which driving current of the same polarity flows, acounter electrode can be used in common between adjacent pixels, makingit possible to reduce the number of slits of the counter electrode. Thatis, polarity inversion can be realized without increasing the resistancevalue of the counter electrodes through which a large current flows.

Furthermore, the construction may be formed in such a way that thepolarity of the driving current in each pixel is inverted for each pixelin both the extension direction of the scanning lines and the extensiondirection of the data lines.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is an illustration schematically showing a display apparatus ofthe present invention, and the formation area of a bank layer formedtherein.

FIG. 2 is a block diagram showing the basic construction of the displayapparatus of the present invention.

FIG. 3 is a plan view in which pixels of the display apparatus accordingto the first embodiment of the present invention are enlarged.

FIG. 4 is a sectional view taken along the line A-A′ of FIG. 3.

FIG. 5 is a sectional view taken along the line B-B′ of FIG. 3.

FIG. 6(A) is a sectional view along the line C-C′ of FIG. 3; and FIG.6(B) is a sectional view of the construction in which the formation areaof a bank layer is not extended until it covers a relay electrode.

FIG. 7 is a graph showing the I-V characteristics of a light-emissionelement used in the display apparatus shown in FIG. 1.

FIGS. 8(A)-(G) include step sectional views showing a method ofmanufacturing a display apparatus of the present invention.

FIG. 9 is a block diagram showing an example of an improvement of thedisplay apparatus shown in FIG. 1.

FIG. 10(A) is a sectional view showing a dummy wiring layer formed inthe display apparatus shown in FIG. 9; and FIG. 10(B) is a plan viewthereof.

FIG. 11 is a block diagram showing a modification of the displayapparatus shown in FIG. 3.

FIG. 12(A) is a plan view in which a pixel formed in the displayapparatus shown in FIG. 11 is enlarged; FIG. 12(B) is a sectional viewthereof.

FIG. 13 is an equivalent circuit diagram showing the construction of twopixels in which the driving current is inverted which are formed in adisplay apparatus according to a second embodiment of the presentinvention.

FIG. 14 is a waveform chart of each signal for driving one of the twopixels shown in FIG. 13.

FIG. 15 is a waveform chart of each signal for driving the other of thetwo pixels shown in FIG. 13.

FIGS. 16(A)-(B) are sectional views showing the construction oflight-emission elements formed in the two pixels shown in FIG. 13.

FIG. 17 includes an illustration showing the arrangement of pixels inthe display apparatus shown in FIG. 13.

FIG. 18 is an illustration showing the arrangement of pixels in adisplay apparatus according to a third embodiment of the presentinvention.

FIG. 19 is an illustration showing the arrangement of pixels in adisplay apparatus according to a fourth embodiment of the presentinvention.

FIG. 20 is an illustration showing the arrangement of pixels in adisplay apparatus according to a fifth embodiment of the presentinvention.

FIG. 21 is an illustration showing the arrangement of pixels in adisplay apparatus according to a sixth embodiment of the presentinvention.

FIG. 22 is a block diagram of a conventional display apparatus.

FIG. 23(A) is a plan view in which a pixel formed in the displayapparatus shown in FIG. 22 is enlarged; FIG. 23(B) is a sectional viewthereof.

DETAILED DESCRIPTIONS OF PREFERRED EMBODIMENTS

The embodiments of the present invention will be described below withreference to the drawings.

[First Embodiment] (Overall construction of active-matrix substrate)

FIG. 1 is a block diagram schematically showing the overall layout of adisplay apparatus. FIG. 2 is an equivalent circuit diagram of an activematrix formed therein.

As shown in FIG. 1, in a display apparatus 1 of this embodiment, thecentral portion of a transparent substrate 10, which is a base bodythereof, is formed into a display section 2. On both ends of the datalines “sig” of the peripheral portion of the transparent substrate 10, adata-side driving circuit 3 for outputting an image signal, and achecking circuit 5 are formed, and on both ends of the scanning lines“gate”, a scanning-side driving circuit 4 for outputting a scanningsignal is formed. In these driving circuits 3 and 4, a complementary TFTis formed by an n-type TFT and a p-type TFT. This complementary TFTforms a shift register, a level shifter, an analog switch, etc. On thetransparent substrate 10, a mounting pad 6, which is a group ofterminals for inputting an image signal, various potentials, and a pulsesignal, is formed in the. peripheral region to the outside from thedata-side driving circuit 3. (Arrangement of common power-feed lines andpixels)

In the display apparatus 1, similarly to an active-matrix substrate of aliquid-crystal display apparatus, on the transparent substrate 10, aplurality of scanning lines “gate”, and a plurality of data lines “sig”which extend in a direction intersecting the extension direction of thescanning lines “gate” are formed. As shown in FIG. 2, these data lines“sig” and scanning lines “gate”. form the pixels 7 in a matrix.

Each of these pixels 7 is formed with a first TFT 20 in which a scanningsignal is supplied to its gate electrode 21 (first gate electrode) viathe scanning lines “gate”. One of the source and drain regions of thesecond TFT 20 is electrically connected to the data line “sig”, and theother is electrically connected to a potential holding electrode “st”.With respect to the scanning lines “gate”. Capacitance lines “cline” aredisposed in parallel, with a holding capacitor “cap” being formedbetween the capacitance line “cline” and the potential holding electrode“st”. Therefore, when the first TFT 20 is selected by the scanningsignal and is turned on, the image signal is written from the data line“sig” into the holding capacitor “cap” via the first TFT 20.

A gate electrode 31 (second gate electrode) of the second TFT 30 iselectrically connected to the potential holding electrode “st”. One ofthe source and drain regions of the second TFT 30 is electricallyconnected to the common power-supply lines “com”, and the other iselectrically connected to one of the electrodes (pixel electrode to bedescribed later) of a light-emission element 40. The common power-supplylines “com” are maintained at a fixed potential. Therefore, when thesecond TFT 30 is turned on, the current in the common power-supply line“com” flows to the light-emission element 40 via this TFT, causing thelight-emission element 40 to emit light.

In this embodiment, on both sides of the common power-feed lines “com”,a plurality of pixels 7 to which driving current is supplied by thecommon power-feed lines “com” are arranged, and two data lines “sig”pass on a side opposite to the common power-feed lines “com” withrespect to these pixels 7. That is, a data line “sig”, a group of pixelsconnected thereto, one common power-feed line “com”, a group of pixelsconnected thereto, and a data line “sig” for supplying a pixel signal tothe group of pixels are assumed to be one unit. This is repeated in theextension direction of scanning lines “gate”, and one common power-feedline “com” is used to supply driving current to the pixels 7 for tworows. Therefore, in this embodiment, in a section between two pixels 7disposed in such a manner as to sandwich the common power-feed lines“com”, the first TFT 20, the second TFT 30, and the light-emissionelements 40 are disposed in linear symmetry about the common power-feedline “com”, simplifying the electrical connection between these elementsand each wiring layer.

As described above, in this embodiment, since pixels for two rows aredriven by one common power-feed line “com”, in comparison with a case inwhich the common power-feed lines “com” are formed for each group ofpixels for one row, one-half of the number of common power-feed lines“com” is required, and the gap secured between the common power-feedlines “com” and the data lines “sig”, which is formed in the samesection between the layers, is not required. Therefore, since an areafor a wiring on the transparent substrate 10 can be made more narrow,the ratio of the light-emission area in each pixel area can be increasedcorrespondingly, making it possible to improve display performance, suchas luminance, contrast ratio, and so on.

Since the construction is formed in such a way that the pixels for tworows are connected to one common power-feed line “com” in this manner,the data lines “sig”, which are in a state of being parallel in groupsof two, supply an image signal to the group of pixels for each row.

(Structure of Pixels)

The structure of each pixel 7 of the display apparatus 1 constructed asdescribed above will be described in detail with reference to FIGS. 3 to6(A).

FIG. 3 is a plan view in which three pixels 7 of the plurality of pixels7 formed in the display apparatus 1 of this embodiment are enlarged.FIGS. 4, 5, and 6(A) are respectively a sectional view along the lineA-A′ of FIG. 3, a sectional view along the line B-B′ of FIG. 3, and asectional view along the line C-C′ of FIG. 3.

First, at a position corresponding to the line A-A′ of FIG. 3, as shownin FIG. 4, in each of the pixels 7 on the transparent substrate 10, anisland-shaped silicon film 200 for forming the first TFT 20 is formed,with a gate insulation film 50 being formed on the surface thereof.Further, a gate electrode 21 (a part of scanning lines “gate” ) isformed on the surface of the gate insulation film 50, and source anddrain regions 22 and 23 are formed so as to be self-aligned with respectto the gate electrode 21. A first interlayer insulation film 51 isformed on the surface of the gate insulation film 50, and the data lines“sig” and the potential holding electrodes “st” are electricallyconnected to the source and drain regions 22 and 23 via contact holes 61and 62 formed on this interlayer insulation film, respectively.

In each pixel 7, capacitance lines “cline” are formed in the samesection between the layers of the scanning lines “gate” and the gateelectrodes 21 (between the gate insulation film 50 and the firstinterlayer insulation film 51) in such a manner as to be parallel to thescanning lines “gate”, and an extended portion “st1” of the potentialholding electrode “st” overlaps this capacitance line “cline” via thefirst interlayer insulation film 51. For this reason, the capacitanceline “cline” and the extended portion “st1” of the potential holdingelectrode “st” form a holding capacitor “cap” in which the firstinterlayer insulation film 51 is a dielectric film. A second interlayerinsulation film 52 is formed on the surface of the potential holdingelectrodes “st” and the data lines “sig”.

At a position corresponding to the line B-B′ in FIG. 3, as shown in FIG.5, two data lines “sig” corresponding to each pixel 7 are parallel onthe surface of the first interlayer insulation film 51 and the secondinterlayer insulation film 52 formed on the transparent substrate 10.

At a position corresponding to the line C-C′ in FIG. 3, as shown in FIG.6(A), an island-shaped silicon film 300 for forming the second TFT 30 isformed on the transparent substrate 10 in such a manner as to extendacross two pixels 7 which sandwich the common power-feed line “com”,with the gate insulation film 50 being formed on the surface thereof. Onthe surface of the gate insulation film 50, the gate electrode 31 isrespectively formed in each of the pixels 7 in such a manner as tosandwich the common power-feed lines “com”, with source and drainregions 32 and 33 being formed so as to be self-aligned in this gateelectrode 31. The first interlayer insulation film. 51 is formed on thesurface of the gate insulation film 50, and the relay electrode 35 iselectrically connected to a source and drain region 32 via a contacthole 63 formed in this interlayer insulation film. In contrast, thecommon power-feed lines “com” are electrically connected to a portion,which is a common source and drain area 33 in two pixels 7 in thecentral portion of the silicon film 300, via a contact hole 64 of thefirst interlayer insulation film 51. A second interlayer insulation film52 is formed on the surface of the common power-feed lines “com” and therelay electrode 35. A pixel electrode 41 formed from an ITO film isformed on the surface of the second interlayer insulation film 52. Thispixel electrode 41 is electrically connected to the relay electrode 35via a contact hole 65 formed in the second interlayer insulation film52, and is electrically connected to the source and drain regions 32 ofthe second TFT 30 via this relay electrode 35.

Here, the pixel electrode 41 forms one of the electrodes of thelight-emission element 40. That is, a positive-hole injection layer 42and an organic semiconductor film 43 are multilayered on the surface ofthe pixel electrode 41, and a counter electrode “op” formed from alithium-containing metal film, such as aluminum or calcium, is formed onthe surface of the organic semiconductor film 43. This counter electrode“op” is a common electrode formed at least on a pixel area or in astripe form, and is maintained at a fixed potential.

In the light-emission element 40 constructed as described above, avoltage is applied by assigning the counter electrode “op” and the pixelelectrode 41 as a positive pole and a negative pole, respectively. Asshown in FIG. 7, the current (driving current) which flows through theorganic semiconductor film 43 increases sharply in an area where theapplied voltage exceeds a threshold voltage. As a result, thelight-emission element 40 emits light as an electroluminescence elementor an LED element. The light from the light-emission element 40 isreflected by the counter electrode “op”, is passed through thetransparent pixel electrode 41 and the transparent substrate 10, and isoutput.

Such driving current used for light emission flows through a currentpath formed of the counter electrode “op”, the organic semiconductorfilm 43, the positive-hole injection layer 42, the pixel electrode 41,the second TFT 30, and the common power-feed lines “com”. Therefore,when the second TFT 30 is turned off, the driving current does not flow.In the display apparatus 1 of this embodiment, when the first TFT 20 isturned on as a result of being selected by a scanning signal, the imagesignal is written from the data lines “sig” into the holding capacitors“cap” via the first TFT 20. Therefore, even if the first TFT 20 isturned off, the gate electrode of the second TFT 30 is maintained at apotential corresponding to the image signal by the holding capacitor“cap”, and therefore, the second TFT 30 remains in an on state.Therefore, the driving current continues to flow through thelight-emission element 40, and this pixel is maintained in a switched-onstate. This state is maintained until new image data is written into theholding capacitor “cap” and the second TFT 30 is turned off.

(Method of Manufacturing Display Apparatus)

In a method of manufacturing the display apparatus 1 constructed asdescribed above, the steps up to manufacturing the first TFT 20 and thesecond TFT 30 on the transparent substrate 10 are nearly the same as thesteps for manufacturing an active-matrix substrate of the displayapparatus 1, and accordingly, are described in general outline withreference to FIGS. 8(A)-(G).

FIGS. 8(A)-(G) include step sectional views schematically showing theprocess of forming each component of the display apparatus 1.

More specifically, as shown in FIG. 8(A), using a TEOS(tetraethoxysilane), oxygen gas, and the like as a starting-material gasas required, a base protective film (not shown) formed from a siliconoxide film having a thickness of approximately 2000 to 5000 angstroms isformed on the transparent substrate 10 by a plasma CVD method. Next, thetemperature of the substrate is set to approximately 350° C., and asemiconductor film 100 formed from an amorphous silicon film having athickness of approximately 300 to 700 angstroms is formed on the surfaceof the base protective film by a plasma CVD method. Next, acrystallization step, such as laser annealing or a solid-phase growthmethod, is performed on the semiconductor film 100 formed from anamorphous silicon film so that the semiconductor film 100 iscrystallized into a polysilicon film. In the laser annealing method, forexample, a line beam forming a spot having a major axis of 400 mm isused in the excimer laser, and its output intensity is, for example, 200mJ/cm². The line beam is scanned in such a way that, for the line beam,a portion corresponding to 90% of the peak value of the laser intensityin the minor axis thereof overlaps in each area.

Next, as shown in FIG. 8(B), the semiconductor film 100 is patternedinto island-shaped silicon films 200 and 300, and a gate insulation film50 formed from a silicon oxide film or a nitride film having a thicknessof approximately 600 to 1500 angstroms is formed on the surface of thesilicon films 200 and 300 by a plasma CVD method by using TEOS(tetraethoxysilane) or oxygen gas as a starting-material gas.

Next, as shown in FIG. 8(C), a conductive film formed from a metal film,such as aluminum, tantalum, molybdenum, titanium, or tungsten, is formedby a sputtering method, after which it is patterned in order to formgate electrodes 21 and 31 as a part of the scanning lines “gate”. Inthis step, the capacitance lines “cline” are also formed. In the figure,reference numeral 310 denotes an extended portion of the gate electrode31.

In this state, high-concentration phosphor ions or boron ions areimplanted to form source and drain regions 22, 23, 32, and 33 in aself-aligned manner with respect to the gate electrodes 21 and 31 in thesilicon thin-films 200 and 300. The portions where impurities are notintroduced become channel areas 27 and 37.

Next, as shown in FIG. 8(D), after the first interlayer insulation film51 is formed, contact holes 61, 62, 63, 64, and 69 are formed, and apotential holding electrode “st” comprising an extended; portion “st1”overlapping the data lines “sig”, the capacitance lines “cline”, and theextended portion 310 of the gate electrode 31, a common power-feed line“com”, and the relay electrode 35 are formed. As a result, the potentialholding electrode “st” is electrically connected to the gate electrode31 via a contact hole 69 and the extended portion 310. In this way, thefirst TFT 20 and the second TFT 30 are formed. Further, the holdingcapacitor “cap” is formed by the capacitance line “cline” and theextended portion “st1” of the potential holding electrode “st”.

Next, as shown in FIG. 8(E), the second interlayer insulation film 52 isformed, and in this interlayer insulation film, a contact hole 65 isformed in a portion corresponding to the relay electrode 35. Next, afterthe ITO film is formed over the entire surface of the second interlayerinsulation film 52, the film is patterned, forming a pixel electrode 41which is electrically connected to the source and drain regions 32 ofthe second TFT 30 via the contact hole 65.

Next, as shown in FIG. 8(F), after a black resist layer is formed on thesurface of the second interlayer insulation film 52, this resist is leftin such a manner as to surround an area where the positive-holeinjection layer 42 and the organic semiconductor film 43 of thelight-emission element 40 should be formed, forming a bank layer “bank”.Here, for the organic semiconductor film 43,: in any shape in a case inwhich the film is formed independently for each pixel, or in a case inwhich the film is formed in a stripe form along the data lines “sig”, amanufacturing method according to this embodiment can be applied bymerely forming the bank layer “bank” in a shape corresponding thereto.

Next, a liquid material (precursor) for forming the positive-holeinjection layer 42 is discharged from an ink-jet head IJ with respect tothe inside area of the bank layer “bank”, and the positive-holeinjection layer 42 is formed in the inside area of the bank layer“bank”. In a similar manner, a liquid material (precursor) for formingthe organic semiconductor film 43 is discharged from the ink-jet head IJwith respect to the inside area of the bank layer “bank”, and theorganic semiconductor film 43 is formed in the inside area of the banklayer “bank”. Here, since the bank layer “bank” is formed from a resist,it is water repellent. In contrast, since the precursor of the organicsemiconductor film 43 mainly uses a hydrophilic solvent, the coatingarea of the organic semiconductor film 43 is reliably defined by thebank layer “bank”, and extrusion into adjacent pixels does not occur.

When forming the organic semiconductor film 43 and the positive-holeinjection layer 42 by an ink-jet method in this manner, in thisembodiment, in order to improve the operation efficiency and theinjection position accuracy, as shown in FIG. 3, the pitch P of thecenters of the formation areas of the organic semiconductor films 43 ismade equal at every interval of the adjacent pixels 7 along theextension direction of the scanning lines “gate”. Therefore, asindicated by the arrow Q, since a material for the organic semiconductorfilm 43 may be discharged from the ink-jet head IJ at positions at evenintervals along the extension direction of the scanning lines “gate”,there is the advantage in that the operation efficiency is superior.Further, the movement control mechanism of the ink-jet head IJ issimplified, and the implantation position accuracy is improved.

Subsequently, as shown in FIG. 8(G), the counter electrode “op” isformed on the surface of the transparent substrate 10. Here, the counterelectrodes “op” are formed at least over the entire surface of the pixelarea or in a stripe form. When the counter electrodes “op” are formed ina stripe form, after a metal film is formed over the entire surface ofthe transparent substrate 10, the metal film is patterned in a stripeform.

Since the bank layer “bank” is formed from a resist, it is left intact,and as will be described below, the layer is used as a black matrix BMand an insulation layer for reducing parasitic capacitance.

TFTs are formed also in the data-side driving circuit 3 and thescanning-side driving circuit 4 shown in FIG. 1. These TFTs are formedby borrowing the entirety or a part of the steps for forming the TFT inthe pixels 7. Therefore, the TFT which forms a driving circuit is alsoformed in the same section between the layers as those of the TFTs ofthe pixels 7.

Further, both the first TFT 20 and the second TFT 30 may be of n-type,or p-type, or one of them may be of n-type and the other of p-type. Inany combination of these cases, TFTs can be formed by a well knownmethod, and accordingly, description thereof has been omitted.(Formation area of bank: layer)

In this embodiment, with respect to the entirety of the peripheral areaof the transparent substrate 10 shown in FIG. 1, the bank layer “bank”(the formation area is shaded) is formed. Therefore, both the data-sidedriving circuit 3 and the scanning-side driving circuit 4 are coveredwith the bank layer “bank”. For this reason, even if the counterelectrodes “op” are in an overlapping state with respect to theformation area of these driving circuits, the bank layer “bank” isinterposed between the wiring layers and the counter electrodes “op” ofthe driving circuits. Therefore, since parasitization of a capacitanceinto the driving circuits 3 and 4 can be prevented, the load of thedriving circuits 3 and 4 can be reduced, thereby making it possible toreduce power consumption or to achieve a higher speed of the displayoperation.

Further, in this embodiment, as shown in FIGS. 3 to 5, the bank layer“bank” is formed so as to overlap the data lines “sig”. Therefore, sincethe bank layer “bank” is interposed between the data lines “sig” and thecounter electrodes “op”, it is possible to prevent capacitance fromparasitizing in the data lines “sig”. As a result, since the load of thedata-side driving circuit 3 can be reduced, power consumption can bereduced or a higher speed of the display operation can be achieved.

Here, unlike the data lines “sig”, a large current for driving thelight-emission elements 40 flows through the common power-feed lines“com”, and the driving current is supplied to the pixels for two rows.For this reason, for the common power-feed lines “com”, their line widthis set to be wider than the line width of the data lines “sig”, and theresistance value per unit length of the common power-feed lines “com” isset to be smaller than the resistance value per unit length of the datalines “sig”. Even under such design conditions, in this embodiment, whenthe bank layer “bank” is formed so as to overlap the common power-feedlines “com” and the formation area of the organic semiconductor film 43is defined, the width of the bank layer “bank” to be formed here is madeat the same width dimension as that of the bank layer “bank” overlappingtwo data lines “sig”, forming a construction suitable for making thepitch P of the centers of the formation areas of the organicsemiconductor films 43 equal at any interval between the adjacent pixels7 along the extension direction of the scanning lines “gate”.

Furthermore, in this embodiment, as shown in FIGS. 3, 4, and 6(A), thebank layer “bank” is also formed in an area overlapping the formationarea of the first TFT 20 and the formation area of the second TFT 30from among the formation area of the pixel electrode 41. That is, asshown in FIG. 6(B), unless the bank layer “bank” is formed in an areaoverlapping the relay electrode 35, even if driving current flows to asection adjoining the counter electrode “op” and the organicsemiconductor film 43 emits light, this light is not output because itis sandwiched between the relay electrode 35 and the counter electrode“op”, and does not contribute to display. Such driving current flowingin a portion which does not contribute to display may be said to be areactive current from the point of view of display. However, in thisembodiment, the bank layer “bank”, is formed in a portion where suchreactive current should flow so that the flowing of the driving currentthereinto is prevented, making it possible to prevent wasteful currentfrom flowing into the common power feed lines “com”. Therefore, thewidth of the common power feed lines “com” may be narrowercorrespondingly.

Also, if the bank layer “bank” which is formed by a black resist asdescribed above remains, the bank layer “bank” functions as a blackmatrix, improving display quality, such as luminance, contrast ratio,etc. That is, in the display apparatus 1 according to this embodiment,since the counter electrodes “op” are formed on the entire surface ofthe transparent substrate 10 or in a stripe form over a wide areathereof, light reflected by the counter electrodes “op” causes thecontrast ratio to decrease. However, in this embodiment, since the banklayer “bank” having the function of inhibiting the parasitic capacitanceis formed by a black resist while defining the formation area of theorganic semiconductor film 43, the bank layer “bank” functions also as ablack matrix, and shuts off reflected light from the counter electrodes“op”, yielding an advantage in that the contrast ratio is high. Further,since the light-emission area can be defined in a self-aligned manner byusing the bank layer “bank”, alignment allowance with the light-emissionarea, which is a problem when the bank layer “bank” is not used as ablack matrix and another metal layer, is used as a black matrix, is notrequired. [Example of an improvement of the above-described embodiment]

In the above-described embodiment, pixels 7, to which driving currentflows in a section between the pixels and the common power-feed lines“com”, are arranged on each of the two sides of the common power-feedlines “com”, and two data lines “sig” pass in parallel on a sideopposite to the common power-feed lines “com” with respect to the pixels7. Therefore, there is a risk that crosstalk might occur between the twodata lines “sig”. Accordingly, in this embodiment, as shown in FIGS. 9,10(A), and 10(B), a dummy wiring layer DA is formed at a positioncorresponding to a section between the two data lines “sig”. As thisdummy wiring layer DA, for example, an ITO film DA1, which is formed atthe same time as the pixel electrode 41, can be used. Further, as thedummy wiring layer DA, an extended portion DA2 from the capacitancelines “cline” may be formed between two data lines “sig”. Both of themmay be used as dummy wiring layer DA.

When the construction is formed in this manner, since a wiring layer DAdifferent from the above passes between two parallel data lines “sig”,the above-mentioned crosstalk can be prevented by merely maintainingsuch wiring layer DA (DA1, DA2) at a fixed potential within at least onehorizontal scanning period of the image. That is, whereas the filmthickness of the first interlayer insulation film 51 and the secondinterlayer insulation film 52 is approximately 1 μm, the intervalbetween two data lines “sig” is approximately 2 μm or more. Therefore,in comparison with capacitance formed between each data line “sig” andthe dummy wiring layer DA (DA1, DA2), the capacitance formed between thetwo data lines “sig” is small enough that it can be effectively ignored.Therefore, since a signal of a high frequency which leaks from the datalines “sig” is absorbed in the dummy wiring layers DA and DA2, crosstalkbetween the two data lines “sig” can be prevented.

Furthermore, between two adjacent data lines “sig” of a plurality ofdata lines “sig”, it is preferable that sampling of an image signal beperformed at the same timing. When the construction is formed in thismanner, since potential variations during sampling occur simultaneouslybetween two data lines “sig”, it is possible to more reliably preventcrosstalk between these two data lines “sig”. [Another example ofconstruction of holding capacitor]

Although in the above-described embodiment, capacitance lines “cline”are formed to form a holding capacitor “cap”, as described in thedescription of the related art, the holding capacitor “cap” may beformed by using a polysilicon film for forming a TFT.

Also, as shown in FIG. 11, the holding capacitor “cap” may be formedbetween the common power-feed line “com” and the potential holdingelectrode “st”. In this case, as shown in FIGS. 12(A) and 12(B), theextended portion 310 of the gate electrode 31 for electricallyconnecting the potential holding electrode “st” to the gate electrode 31may be extended to the side of the lower layers of the common power-feedlines “com”, and the holding capacitor “cap” may be formed by using thefirst interlayer insulation film 51 positioned between this extendedportion 310 and the common power-feed line “com” as a dielectric film.

[Second Embodiment]

Although in the above-described first embodiment, the construction isformed in such a way that the light-emission elements 40 are driven bydriving current of the same polarity in any pixel 7, as will bedescribed below, the construction may be formed in such a way that thesame number of two types of pixels 7, in which the light-emissionelements 40 are driven by a driving current whose polarity is inverted,are among a plurality of pixels 7 to which driving current is passed ina section between the pixels and the same common power-feed line “com”.

Examples of such constructions are described with reference to FIGS. 13to 17. FIG. 13 is a block diagram of an embodiment in which two types ofpixels, in which the light-emission elements 40 are driven by a drivingcurrent whose polarity is inverted, are structured. FIGS. 14 and 15 areeach an illustration of a scanning signal, an image signal, thepotential of common power-feed lines, and a potential of a potentialholding electrode when the light-emission element 40 is driven by adriving current whose polarity is inverted.

In this embodiment and the embodiments to be described later, as shownin FIG. 13, when driving the light-emission element 40 by drivingcurrent i whose polarity is inverted, in a pixel 7A to which drivingcurrent flows from the common power-feed lines “com” as indicated by anarrow E, the first TFT 20 is formed of an n-channel type, and in a pixel7B from which driving current flows to the common power-feed lines “com”as indicated by an arrow F, the first TFT 20 is formed of a p-channeltype. For this reason, a scanning line “gateA” and a scanning line“gateB” are formed in these two types of pixels 7A and 7B, respectively.Also, in this embodiment, if the second TFT 30 of the pixel 7A is formedof a p-channel type, the second TFT 30 of the pixel 7B is formed of ann-channel type, the first TFT 20 and the second TFT 30 being formed tobe a reverse-conduction type in each of the pixels 7A and 7B. Therefore,for the image signals supplied respectively via a data line “sigA”corresponding to the pixel 7A and a data line “sigB” corresponding tothe pixel 7B, their polarities are inverted, as will be described later.

Furthermore, in each of the pixels 7A and 7B, since the light-emissionelement 40 is driven by the driving current i whose polarity isinverted, as described later, the construction must be formed in such away that the potential of the counter electrode “op” also has anopposite polarity when the potential of the common power-feed line “com”is used as a reference. Therefore, the counter electrode “op” is formedin such a way that the pixels 7A and 7B, to which the driving current ihaving the same polarity flows, are connected together and apredetermined potential is applied to each of them.

Therefore, as shown in FIGS. 14 and 15, for the pixels 7A and 7B,waveforms of scanning signals supplied via the scanning lines “gateA”and “gateB”, waveforms of image signals supplied via the data lines“sigA” and “sigB”, the potential of the counter electrode “op”, thepotentials of potential holding electrodes “stA” and “stB” are shown byusing the potential of the common power-feed lines “com” as a reference,respectively. Between the pixels 7A and 7B, each signal is set to havean opposite polarity in both the switched-on period and the switched-offperiod.

Also, as shown in FIGS. 16(A) and 16(B), light-emission elements 40A and40B of different constructions are formed in the pixels 7A and 7B,respectively. That is, in the light-emission element 40A formed in thepixel 7A, from the side of the lower layers toward the side of the upperlayers, the pixel electrode 41 formed from an ITO film, thepositive-hole injection layer 42, the organic semiconductor film 43, andthe counter electrode “opA” are multilayered in this sequence. Incontrast, in the light-emission element 40B formed in the pixel 7B, fromthe side of the lower layers toward the side of the upper layers, thepixel electrode 41 formed from an ITO film, a lithium-containingaluminum electrode 45, which is so thin as to have a light transmissionproperty, the organic semiconductor film 43, the positive-hole injectionlayer 42, an ITO film layer 46, and a counter electrode “opB” aremultilayered in this sequence. Therefore, even though driving current ofan opposite polarity flows through the light-emission elements 40A and40B, respectively, since the structures of the electrode layers withwhich the positive-hole injection layer 42 and the organic semiconductorfilm 43 are in direct contact are the same, the light-emissioncharacteristics of the light-emission elements 40A and 40B areidentical.

When forming such two types of light-emission elements 40A and 40B,since each of both the organic semiconductor film 43 and thepositive-hole injection layer 42 is formed in the inside of the banklayer “bank” by an ink-jet method, even if the top and bottom positionsare reversed, the manufacturing steps are not complex. Further, in thelight-emission element 40B, in comparison with the light-emissionelement 40A, the lithium-containing aluminum electrode 45, which is sothin as to have a light transmission property, and the ITO film layer 46are added. Nevertheless, even if the lithium-containing aluminumelectrode 45 is structured so as to be multilayered in the same area asthat of the pixel electrode 41, no problem is posed for the display, andeven if the ITO film layer 46 is also structured so as to bemultilayered in the same area as that of the counter electrode “opB”, noproblem is posed for the display. Therefore, the lithium-containingaluminum electrode 45 and the pixel electrode 41 may be patternedindependently of each other, but may be patterned collectively by thesame resist mask. In a similar manner, the ITO film layer 46 and thecounter electrode “opB” may be patterned independently of each other,but may be patterned collectively by the same resist mask. It is amatter of course that the lithium-containing aluminum electrode 45 andthe ITO film layer 46 may be formed only within the inside area of thebank layer “bank”.

After the light-emission elements 40A and 40B are made to be capable ofbeing driven by a driving current whose polarity is inverted in each ofthe pixels 7A and 7B in this manner, the two types of pixels 7A and 7Bare arranged as shown in FIG. 17. In this figure, the pixel given thesign (−) corresponds to the pixel 7A described with reference to FIGS.13, 14, and 16, and the pixel given the sign (+) corresponds to thepixel 7B described with reference to FIGS. 13, 15, and 16. In FIG. 17,the illustration of the scanning lines “gateA” and “gate”, and the datalines “sigA” and “sigB” is omitted.

As shown in FIG. 17, in this embodiment, the polarity of the drivingcurrent in each pixel is the same along the extension direction of thedata lines “sigA” and “sigB”, and along the extension direction of thescanning lines “gateA” and “gateB”, the polarity of the driving currentin each pixel is inverted for each pixel. As the formation areas of thecounter electrodes “opA” and “opB” corresponding to each pixel areindicated by a dotted-chain line, respectively, each of the counterelectrodes “opA” and “opB” is constructed so as to connect together thepixels 7A and 7B to which driving current having the same polarityflows. That is, the counter electrodes “opA” and “opB” are formed in astripe form independently of each other along the extension direction ofthe data lines “sigA” and “sigB”, and a negative potential and apositive potential when the potential of the common power-feed line“com” is used as a reference are applied to the counter electrodes “opA”and “opB”, respectively.

Therefore, between each of the pixels 7A and 7B and the commonpower-feed line “com”, driving currents i in a direction indicated byarrows E and F in FIG. 13 flow, respectively. For this reason, since thecurrent which flows substantially through the common power-feed line“com” is cancelled by the driving current i of a different polarity, asmaller amount of the driving current flowing through the commonpower-feed lines “com” is required. Therefore, since the commonpower-feed lines “com” can be made correspondingly narrower, it ispossible to increase the ratio of the light-emission area of the pixelarea in the pixels 7A and 7B and to improve display performance, such asluminance, contrast ratio, and so on.

[Third Embodiment]

From the viewpoint of the fact that pixels are arranged in such a waythat driving current flows at an opposite polarity in a section betweenthe pixels and the same common power-feed line “com”, each pixel may bearranged as shown in FIG. 18. In this embodiment, since the constructionof each of the pixels 7A and 7B is similar to that of the secondembodiment. Therefore, the description has been omitted. In FIG. 18 andFIGS. 19 to 21, for describing each embodiment to be described below, apixel corresponding to the pixel 7A described with reference to FIGS.13, 14, and 16 is shown by the sign (−), and a pixel corresponding tothe pixel 7B described with reference to FIGS. 13, 15, and 16 is shownby the sign (+).

As shown in FIG. 18, in this embodiment, the construction is formed insuch a way that the polarity of the driving current in each of thepixels 7A and 7B is the same along the extension direction of the datalines “sigA” and “sigB” and that along the extension direction of thescanning lines “gateA” and “gateB”, the polarity of the driving currentin each of the pixels 7A and 7B is inverted every two pixels.

Also when the construction is formed in this manner, driving current iin a direction indicated by arrows E and F in FIG. 13 flows between eachof the pixels 7A and 7B and the common power-feed line “com”,respectively. For this reason, since the current which flows through thecommon power-feed line “com” is cancelled by the driving current i of adifferent polarity, a smaller amount of the driving current flowingthrough the common power-feed lines “com” is required. Therefore, sincethe common power-feed lines “com” can be made correspondingly narrower,it is possible to increase the ratio of the light-emission area of thepixel area in the pixels 7A and 7B of the pixel area and to improvedisplay performance, such as luminance, contrast ratio, and so on. Inaddition, in this embodiment, since the polarity of the driving currentis inverted every two pixels along the extension direction of thescanning lines “gateA” and “gateB”, for the pixels which are driven bydriving current having the same polarity, the counter electrodes “opA”and “opB” which are common to the adjacent pixels for two rows may beformed in a stripe form. Therefore, the number of stripes of the counterelectrodes “opA” and “opB” can be reduced by half. Further, since theresistance of the counter electrodes “opA” and “opB” can be decreased incomparison with the stripe for each pixel, an influence of a voltagedrop of the counter electrodes “opA” and “opB” can be reduced.

[Fourth Embodiment]

Furthermore, from the viewpoint of the fact that pixels are arranged insuch a way that driving current flows at an opposite polarity in asection between the pixels and the same common power-feed line “com”,each pixel may be arranged as shown in FIG. 19.

As shown in FIG. 19, in this embodiment, the construction is formed insuch a way that the polarity of the driving current in each of thepixels 7A and 7B is the same along the extension direction of thescanning lines “gateA” and “gateB” and that along the extensiondirection of the data lines “sigA” and “sigB”, the polarity of thedriving current in each of the pixels 7A and 7B is inverted for eachpixel.

Also in the case where the construction is formed in this manner,similarly to the second embodiment or the third embodiment, since thecurrent flowing through the common power-feed lines “com” is cancelledby the driving current having a different polarity, a smaller amount ofthe driving current flowing through the common power-feed lines “com” isrequired. Therefore, since the common power-feed lines “com” can be madecorrespondingly narrower, it is possible to increase the ratio of thelight-emission area of the pixel area in the pixels 7A and 7B and toimprove display performance, such as luminance, contrast ratio, and soon.

[Fifth Embodiment]

Furthermore, from the viewpoint of the fact that pixels are arranged insuch a way that driving current flows at an opposite polarity in asection between the pixels and the same common power-feed line “com”,each pixel may be arranged as shown in FIG. 20.

As shown in FIG. 20, in this embodiment, the construction is formed insuch a way that the polarity of the driving current in each of thepixels 7A and 7B is the same along the extension direction of thescanning lines “gateA” and “gateB” and that along the extensiondirection of the data lines “sigA” and “sigB”, the polarity of thedriving current in each of the pixels 7A and 7B is inverted every twopixels.

When the construction is formed in this manner, similarly to the thirdembodiment, since the current which flows through the common power-feedline “com” is cancelled by the driving current of a different polarity,a smaller amount of the driving current flowing through the commonpower-feed lines “com” is required. Therefore, since the commonpower-feed lines “com” can be made correspondingly narrower, it ispossible to increase the ratio of the light-emission area of the pixelarea in the pixels 7A and 7B and to improve display performance, such asluminance, contrast ratio, and so on. In addition, in this embodiment,since the polarity of the driving current is inverted every two pixelsalong the extension direction of the data lines “sigA” and “sigB”, forthe pixels which are driven by the driving current having the samepolarity, the counter electrodes “opA” and “opB” which are common to theadjacent pixels for two rows may be formed in a stripe form. Therefore,the number of stripes of the counter electrodes “opA” and “opB” can bereduced by half. Further, since the resistance of the counter electrodes“opA” and “opB” can be decreased in comparison with the stripe for eachpixel, an influence of a voltage drop of the counter electrodes “opA”and “opB” can be reduced.

[Sixth Embodiment]

Furthermore, from the viewpoint of the fact that pixels are arranged insuch a way that driving current flows at an opposite polarity in asection between the pixels and the same common power-feed line “com”,each pixel may be arranged as shown in FIG. 21.

As shown in FIG. 21, in this embodiment, the construction is formed insuch a way that the polarity of the driving current in each of thepixels 7A and 7B is inverted for each pixel along both the extensiondirection of the scanning lines “gateA” and “gateB” and the extensiondirection of the data lines “sigA” and “sigB”.

Also in the case where the construction is formed in this manner,similarly to the second to fourth embodiments, since the current flowingthrough the common power-feed lines “com” is cancelled by the drivingcurrent having a different polarity, a smaller amount of the drivingcurrent flowing through the common power-feed lines “com” is required.Therefore, since the common power-feed lines “com” can be madecorrespondingly narrower, it is possible to increase the ratio of thelight-emission area in the pixels 7A and 7B and to improve displayperformance, such as luminance, contrast ratio, and so on.

When the pixels 7A and 7B are arranged in this manner, the counterelectrodes “opA” and “opB” in a stripe form cannot cope. Nevertheless,the construction may be formed in such a way that the counter electrodes“opA” and “opB” are formed for each of the pixels 7A and 7B,respectively, and that the counter electrodes “opA” and “opB” areconnected by a wiring layer.

Industrial Applicability

As has been described up to this point, in the display apparatusaccording to the present invention, since pixels to which drivingcurrent is passed in a section between the pixels and the commonpower-feed line are arranged on both sides of the common power-feedline, only one common power-feed line is required for pixels for tworows. Therefore, since the formation area of the common power-feed lines“com” can be made narrower in comparison with a case where the commonpower-feed line is formed for each group of pixels for one row, it ispossible to increase correspondingly the ratio of the light-emissionarea in the pixels and to improve display performance, such asluminance, contrast ratio, and so on.

When two types of pixels in which the light-emission element are drivenby a driving current whose polarity is inverted are among a plurality ofpixels to which the driving current is passed in a section between thepixels and the same common power-feed line, in one common power-feedline, since driving current flowing from the common power-feed line tothe light-emission element cancels the driving current flowing in anopposite direction from the light-emission element to the commonpower-feed line, a smaller amount of the driving current which flowsthrough the common power-feed line is required. Therefore, since thecommon power-feed lines “com” can be made correspondingly narrower, itis possible to increase the ratio of the light-emission area in thepixels and to improve display performance, such as luminance, contrastratio, and so on.

What is claimed is:
 1. A display apparatus comprising: a plurality ofscanning lines; a plurality of data lines; a plurality of commonpower-feed lines; a plurality of pixels corresponding to intersectionsof the plurality of scanning lines and the plurality of data lines, onepixel of the plurality of pixels comprising: a first transistor having afirst gate electrode connected to one scanning line of the plurality ofscanning lines; a holding capacitor that holds a signal supplied fromone data line of the plurality of data lines via the first transistor; asecond transistor having a second gate electrode connected to theholding capacitor; and a light-emission element having an organicsemiconductor film which emits a light by a driving current that flowsbetween a pixel electrode and counter electrode when the pixel electrodeis electrically connected to a corresponding common power-feed line ofthe plurality of common power-feed lines, the organic semiconductor filmbeing surrounded by a bank layer, the one data line passing on a sideopposite to the corresponding common power-feed line with respect to theone pixel; and the bank layer overlapping the corresponding commonpower-feed line.
 2. The display apparatus according to claim 1, thecorresponding common power-feed line being disposed in such a mannerthat the corresponding common power-feed line is sandwiched between theone pixel and another pixel.
 3. The display apparatus according to claim2, the first transistor in the one pixel and a first transistor in theanother pixel, the second transistor in the one pixel and a secondtransistor in the another pixel, and the light emission-element in theone pixel and a light-emission element in the another pixel beingdisposed in linear symmetry with respect to the correspondingcommon-feed line, respectively.
 4. The display apparatus according toclaim 1, the plurality of pixels including a set of pixels each of whichhas a light-emission element disposed along one of the scanning lines,every pixel of the set of pixels being disposed in such a manner that aninterval between centers of organic semiconductor films included inlight-emission elements of every two adjacent pixels of the set ofpixels is the same.
 5. The display apparatus according to claim 1, thebank layer overlapping the one data line of the plurality of data lines.6. The display apparatus according to claim 1, the organic semiconductorfilm being formed by an ink-jet method.
 7. The display apparatusaccording to claim 1, further comprising a wiring layer being disposedbetween two adjacent data lines of the plurality of data lines.
 8. Thedisplay apparatus according to claim 7, sampling of a signal at the twoadjacent data lines being performed at the same time.
 9. The displayapparatus according to claim 1, a polarity of a driving current drivingthe light-emission element of the one pixel being inverted to a polarityof a driving current driving a light-emission element of the anotherpixel.
 10. The display apparatus according to claim 1, the plurality ofpixels including a set of pixels having light-emission elements disposedalong one of the plurality of scanning lines, a polarity of a drivingcurrent driving a light-emission element of each pixel of the set ofpixels being inverted to a polarity of a driving current alight-emission element of a pixel adjacent to each pixel of the set ofpixels.
 11. The display apparatus according to claim 1, the plurality ofpixels including a set of pixels having light-emission elements disposedalong one of the plurality of scanning lines, a polarity of a drivingcurrent driving light-emission elements of every two pixels of the setof pixels being the same.
 12. The display apparatus according to claim1, the plurality of pixels including a set of pixels havinglight-emission elements disposed along one of the plurality of datalines, a polarity of a driving current driving a light-emission elementof each pixel of the set of pixels being inverted to a polarity of adriving current of a light-emission element of a pixel adjacent to eachpixel of the set of pixels.
 13. The display apparatus according to claim1, the plurality of pixels including a set of pixels havinglight-emission elements disposed along one of the plurality of datalines, a polarity of a driving current driving light-emission elementsof every two pixels of the set of pixels being the same.
 14. The displayapparatus according to claim 1, a polarity of a driving current drivinglight-emission element of each pixel of a set of pixels havinglight-emission elements of the plurality of pixels being inverted to apolarity of a driving current a light-emission element of all pixelsadjacent to each pixel of the set of pixels.
 15. A display apparatuscomprising: a plurality of scanning lines; a plurality of data lines; aplurality of common power-feed lines; a plurality of pixelscorresponding to intersections of the plurality of scanning lines andthe plurality of data lines; one pixel of the plurality of pixelscomprising: a first transistor having a first gate electrode connectedto one scanning line of the plurality of scanning lines; a holdingcapacitor that holds a signal supplied from one data line of theplurality of data lines via the first transistor; a second transistorhaving a second gate electrode connected to the holding capacitor; and alight-emission element having an organic semiconductor film which emitsa light by a driving current that flows between a pixel electrode andcounter electrode when the pixel electrode is electrically connected toa corresponding common power-feed line of the plurality of commonpower-feed lines, the organic semiconductor film being surrounded by abank layer; at least a part of the bank layer overlapping thecorresponding common power-feed line.
 16. The display apparatusaccording to claim 15, at least a part of the bank layer overlapping theone data line.
 17. The display apparatus according to claim 15, thecorresponding common power-feed line being disposed in such a mannerthat the corresponding common power-feed line is sandwiched between theone pixel and another pixel.
 18. A display apparatus comprising: aplurality of scanning lines; a plurality of data lines; a plurality ofcommon power-feed lines; a plurality of pixels corresponding tointersections of the plurality of scanning lines and the plurality ofdata lines; one pixel of the plurality of pixels comprising: a firsttransistor having a first gate electrode connected to one scanning lineof the plurality of scanning lines; a holding capacitor that holds asignal supplied from one data line of the plurality of data lines viathe first transistor; a second transistor having a second gate electrodeconnected to the holding capacitor; and a light-emission element havingan organic semiconductor film which emits a light by a driving currentthat flows between a pixel electrode and counter electrode when thepixel electrode is, electrically connected to a corresponding commonpower-feed line of the plurality of common power-feed lines, the organicsemiconductor film being surrounded by a bank layer; the one data linepassing on a side opposite to the corresponding common power-feed linewith respect to the one pixel; and the line width of the correspondingcommon power-feed line being set to be wider than that of the one dataline.
 19. The display apparatus according to claim 18, the correspondingcommon power-feed line being disposed in such a manner that thecorresponding common power-feed line is sandwiched between the one pixeland another pixel.
 20. The display apparatus according to claim 18, atleast a part of the bank layer overlapping the corresponding commonpower-feed line.
 21. The display apparatus according to claim 18, atleast a part of the bank layer overlapping the one data line.
 22. Adisplay apparatus comprising: a plurality of scanning lines; a pluralityof data lines; a plurality of common power-feed lines; a plurality ofpixels corresponding to intersections of the plurality of scanning linesand the plurality of data lines; one pixel of the plurality of pixelscomprising: a first transistor having a first gate electrode connectedto one scanning line of the plurality of scanning lines; a holdingcapacitor that holds a signal supplied from one data line of theplurality of data lines via the first transistor; a second transistorhaving a second gate electrode connected to the holding capacitor; and alight-emission element having an organic semiconductor film which emitsa light by a driving current that flows between a pixel electrode andcounter electrode when the pixel electrode is electrically connected toa corresponding common power-feed line of the plurality of commonpower-feed lines, the organic semiconductor film being surrounded by abank layer; the line width of the corresponding common power-feed linebeing set to be wider than that of the one data line.
 23. The displayapparatus according to claim 22, at least a part of the bank layeroverlapping the corresponding common power-feed line.
 24. The displayapparatus according to claim 22, at least a part of the bank layeroverlapping the one data line.